Memory Chip Design
Q22.
A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes 100 nsec. What percentage of the memory cycle time is used for refreshing?Q23.
What is the minimum size of ROM required to store the complete truth table of an 8-bit \times 8-bit multiplier?Q24.
Number of chips (128 \times 8 RAM) needed to provide a memory capacity of 2048 bytesQ26.
A main memory unit with a capacity of 4 megabytes is built using 1Mx1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit isQ27.
A ROM is used to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required isQ28.
The process of organizing the memory into two banks to allow 8-and 16-bit data operation is calledQ29.
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: The advantages of CMOS technology over a MOS is:Q30.
The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of 4K \times 16?